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XC4VLX60-10FF1148C 500MHz 640 I/O Xilinx Virtex 4

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XC4VLX60-10FF1148C 500MHz 640 I/O Xilinx Virtex 4

Brand Name : Xilinx Inc.

Model Number : XC4VLX60-10FF1148C

Certification : Lead free / RoHS Compliant

MOQ : 1 pcs

Price : USD 1000~2200 pcs

Payment Terms : T/T, Western Union, Paypal, Trade Assurance, Credit Card

Supply Ability : 92 pcs

Delivery Time : 3-5 Day

Packaging Details : International Standard Packaging

Category : Programmable Logic ICs

Condition : Original 100%,Brand New and Original,New

Number of I/Os : 640 I/O

Product : Virtex-4

Package / Case : FBGA-1148

Distributed RAM : 416 kbit

Embedded Block RAM - EBR : 2880 kbit

Maximum Operating Frequency : 500 MHz

Service : BOM Kitting

Lead time : In Stock,contact us

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XC4VLX60-10FF1148C IC FPGA FBGA-1148 640 I/O 500 MHz Virtex-4

 

Product Attribute Attribute Value
Xilinx
FPGA - Field Programmable Gate Array
Virtex-4
59904
640 I/O
1.2 V
0 C
+ 85 C
SMD/SMT
FCBGA-1148
Series: XC4VLX60
Brand: Xilinx
Distributed RAM: 416 kbit
Embedded Block RAM - EBR: 2880 kbit
Maximum Operating Frequency: 500 MHz
Moisture Sensitive: Yes
Product Type: FPGA - Field Programmable Gate Array
Factory Pack Quantity: 1
Subcategory: Programmable Logic ICs
Tradename: Virtex

 

Summary of Virtex-4 FPGA Features

 

The wide array of Virtex-4 FPGA hard-IP core blocks includes the PowerPC® processors (with a new APU interface),
tri-mode Ethernet MACs, 622 Mb/s to 6.5 Gb/s serial transceivers, dedicated DSP slices, high-speed clock management circuitry,
and source-synchronous interface blocks. The basic Virtex-4 FPGA building blocks are enhancements of those found in the popular
Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X product families, so previous-generation designs are upward compatible.
Virtex-4 devices are produced on astate-of-the-art 90 nm copper process using 300 mm (12-inch) wafer technology
 
• Smart RAM Memory Hierarchy
- Distributed RAM
- Dual-port 18-Kbit RAM blocks
· Optional pipeline stages
· Optional programmable FIFO logic automatically remaps RAM signals as FIFO signals
- High-speed memory interface supports DDR and DDR-2 SDRAM, QDR-II, and RLDRAM-II.

• True differential termination
• Selected low-capacitance I/Os for improved signal integrity
• Same edge capture at input and output I/Os
• Memory interface support for DDR and DDR-2 SDRAM, QDR-II, and RLDRAM-II.

• Smart RAM Memory Hierarchy
- Distributed RAM
- Dual-port 18-Kbit RAM blocks
· Optional pipeline stages
· Optional programmable FIFO logic automatically remaps RAM signals as FIFO signals
- High-speed memory interface supports DDR and DDR-2 SDRAM, QDR-II, and RLDRAM-II.

 

 

XC4VLX60-10FF1148C 500MHz 640 I/O Xilinx Virtex 4


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500MHz xilinx virtex

      

640 I/O xilinx virtex 4

      
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