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3.3V ALTERA FPGA Chip

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3.3V ALTERA FPGA Chip

Name: 33V ALTERA FPGA Chip
Brand: Intel / Altera
Price: 3000 USD

Brand Name : Intel / Altera

Model Number : EP2AGZ300FF35C4N

Certification : Lead free / RoHS Compliant

MOQ : 1 pcs

Price : USD 3000-5000 pcs

Payment Terms : T/T, Western Union, Paypal, Trade Assurance, Credit Card

Supply Ability : 226 pcs

Delivery Time : 3-5 Day

Packaging Details : International Standard Packaging

Category : IC FPGA

Condition : Original 100%,Brand New and Original,New

Series : Arria II GZ

Number of Logic Array Blocks - LABs : 11920

Number of I/Os : 554 I/O

Operating Supply Voltage : 1.5 V to 3.3 V

Package / Case : FBGA-1152

Data Rate : 600 Mb/s to 6.375 Gb/s

Service : BOM Kitting

Lead time : In Stock,contact us

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EP2AGZ300FF35C4N ALTERA FPGA Chip FBGA-1152 554 I/O Arria II GZ

Product Attribute	Attribute Value
Manufacturer:	Intel
Product Category:	FPGA - Field Programmable Gate Array
Product:	Arria II GZ
Number of Logic Elements:	298000
Number of Logic Array Blocks - LABs:	11920
Number of I/Os:	554 I/O
Operating Supply Voltage:	1.5 V to 3.3 V
Minimum Operating Temperature:	0 C
Maximum Operating Temperature:	+ 70 C
Mounting Style:	SMD/SMT
Package / Case:	FBGA-1152
Packaging:	Tray
Data Rate:	600 Mb/s to 6.375 Gb/s
Series:	Arria II GZ
Brand:	Intel / Altera
Embedded Block RAM - EBR:	3725 kbit
Maximum Operating Frequency:	540 MHz
Moisture Sensitive:	Yes
Number of Transceivers:	16/24 Transceiver
Product Type:	FPGA - Field Programmable Gate Array
Factory Pack Quantity:	24
Subcategory:	Programmable Logic ICs
Total Memory:	18413 kbit
Tradename:	Arria
Part # Aliases:	969699

■ Arria II GX devices have dedicated configuration banks at Bank 3C and 8C, which support dedicated configuration pins and some of the dual-purpose pins with a
configuration scheme at 1.8, 2.5, 3.0, and 3.3 V. For Arria II GZ devices, the dedicated configuration pins are located in Bank 1A and Bank 1C. However, these
banks are not dedicated configuration banks; therefore, user I/O pins are available in Bank 1A and Bank 1C.
■ Dedicated VCCIO, VREF, and VCCPD pin per I/O bank to allow voltage-referenced I/O standards. Each I/O bank can operate at independent VCCIO, VREF, and
VCCPD levels.

High-Speed LVDS I/O and DPA
■ Dedicated circuitry for implementing LVDS interfaces at speeds from 150 Mbps to 1.25 Gbps
■ RD OCT for high-speed LVDS interfacing
■ DPA circuitry and soft-CDR circuitry at the receiver automatically compensates for channel-to-channel and channel-to-clock skew in source-synchronous interfaces
and allows for implementation of asynchronous serial interfaces with embedded clocks at up to 1.25 Gbps data rate (SGMII and GbE)
■ Emulated LVDS output buffers use two single-ended output buffers with an external resistor network to support LVDS, mini-LVDS, BLVDS (only for
Arria II GZ devices), and RSDS standards.

3.3V ALTERA FPGA Chip

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